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| TC7MH373FK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC7MH373FK Octal D-Type Latch with 3-State Output The TC7MH373FK is an advanced high speed CMOS octal latch with 3-state output fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent bipolar schottky TTL while marinating the CMOS low power dissipation. This 8 bit D-type latch is controlled by a latch enable input (LE) and a output enable input ( OE ). When the OE input is high, the eight outputs are in a high impedance state. Weight: 0.03 g (typ.) An input protection circuit ensures the 0 to 7 V can be applied to the input pins can be used to interface 5 V to 3 V systems and two supply systems such as battery back up. This circuit prevents destruction due to mismatched supply and input voltages. Features * * * * * * * * High speed: tpd = 5.0 ns (typ.) (VCC = 5 V) Low power dissipation: ICC = 4 A (max) (Ta = 25C) High noise immunity: VNIH = VNIL = 28% VCC (min) Power down protection is provided on all inputs. Balanced propagation delays: tpLH tpHL - Wide operating voltage range: VCC (opr) = 2~5.5 V Low noise: VOLP = 0.8 (max) Pin and function compatible with 74ALS373 000630EBA1 * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The Toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These Toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of Toshiba products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice. 2000-07-04 1/7 TC7MH373FK Pin Assignment (top view) IEC Logic Symbol OE LE (1) (11) EN C1 OE 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 11 VCC Q7 D7 D6 Q6 Q5 Q0 D0 D1 Q1 Q2 D2 D3 Q3 D0 D1 D2 D3 D4 (3) (4) (7) (8) (13) (14) (17) (18) 1D (2) (5) (6) (9) (12) (15) (16) (19) Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D5 D4 Q4 LE D5 D6 D7 GND 10 Truth Table Inputs OE Outputs D X X L H Z Qn L H LE X L H H H L L L X: Don't care Z: High impedance Qn: Q outputs are latched at the time when the LE input is taken to a low logic level. System Diagram D0 3 D D1 4 D D2 7 D D3 8 D D4 13 D D5 14 D D6 17 D D7 18 D 11 LE L Q L Q L Q L Q L Q L Q L Q L Q 1 OE 2 Q0 5 Q1 6 Q2 9 Q3 12 Q4 15 Q5 16 Q6 19 Q7 2000-07-04 2/7 TC7MH373FK Maximum Ratings Characteristics Supply voltage range DC input voltage DC output voltage Input diode current Output diode current DC output current DC VCC/ground current Power dissipation Storage temperature Symbol VCC VIN VOUT IIK IOK IOUT ICC PD Tstg Rating -0.5~7.0 -0.5~7.0 -0.5~VCC + 0.5 -20 20 25 75 180 -65~150 Unit V V V mA mA mA mA mW C Recommended Operating Conditions Characteristics Supply voltage Input voltage Output voltage Operating temperature Input rise and fall time Symbol VCC VIN VOUT Topr dt/dv Rating 2.0~5.5 0~5.5 0~VCC -40~85 0~100 (VCC = 3.3 0.3 V) 0~20 (VCC = 5 0.5 V) Unit V V V C ns/V 2000-07-04 3/7 TC7MH373FK Electrical Characteristics DC Characteristics Characteristics Symbol Test Condition VCC (V) 2.0 High level Input voltage 2.0 Low level VIL 3.0~5.5 2.0 VIN = VIH or VIL IOH = -50 A 3.0 4.5 IOH = -4 mA Output voltage VIN = VIH or VIL IOH = -8 mA IOL = 50 A IOL = 4 mA IOL = 8 mA 3-state output off-state current Input leakage current Quiescent supply current IOZ IIN ICC VIN = VIH or VIL VOUT = VCC or GND VIN = 5.5 V or GND VIN = VCC or GND 3.0 4.5 2.0 3.0 4.5 3.0 4.5 5.5 0~5.5 5.5 VIH 3.0~5.5 Min 1.50 VCC x 0.7 1.9 2.9 4.4 2.58 3.94 Ta = 25C Typ. 2.0 3.0 4.5 0 0 0 Max 0.50 VCC x 0.3 0.1 0.1 0.1 0.36 0.36 0.25 0.1 4.0 Ta = -40~85C Min 1.50 VCC x 0.7 1.9 2.9 4.4 2.48 3.80 Max V 0.50 VCC x 0.3 0.1 0.1 0.1 0.44 0.44 2.50 1.0 40.0 A A A V Unit High level VOH Low level VOL 2000-07-04 4/7 TC7MH373FK Timing Requirements (Input: tr = tf = 3 ns) Characteristics Minimum pulse width (LE) Minimum set-up time Symbol Test Condition VCC (V) tw (H) 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 Ta = 25C Typ. Limit 5.0 5.0 4.0 4.0 1.0 1.0 Ta = -40~85C Limit 5.0 5.0 4.0 4.0 1.0 1.0 ns ns ns Unit ts Minimum hold time th AC Characteristics (Input: tr = tf = 3 ns) Characteristics Symbol Test Condition VCC (V) CL (pF) 3.3 0.3 tpLH tpHL 5.0 0.5 15 50 15 50 15 50 15 50 15 50 15 50 50 50 50 50 Min (Note2) Ta = 25C Typ. 7.0 9.5 4.9 6.4 7.3 9.8 5.0 6.5 7.3 9.8 5.5 7.0 9.5 6.5 4 6 27 Max 11.0 14.5 7.2 9.2 11.4 14.9 7.2 9.2 11.4 14.9 8.1 10.1 13.2 9.2 1.5 1.0 10 Ta = -40~85C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 13.0 16.5 8.5 10.5 13.5 17.0 ns 8.5 10.5 13.5 17.0 ns 9.5 11.5 15.0 10.5 1.5 1.0 10 pF pF pF ns ns ns Unit Propagation delay time (LE-Q) Propagation delay time (D-Q) 3.3 0.3 tpLH tpHL 5.0 0.5 3-state output enable time tpZL tpZH 3.3 0.3 RL = 1 k 5.0 0.5 3.3 0.3 5.0 0.5 (Note1) 3.3 0.3 5.0 0.5 3-state output disable time tpLZ tpHZ RL = 1 k Output to output skew Input capacitance Bus input capacitance Power dissipation capacitance tosLH tosHL CIN COUT CPD Note1: This parameter is guaranteed by design. tosLH = |tpLHm - tpLHn|, tosHL = |tpHLm - tpHLn| Note2: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) = CPD VCC fIN + ICC/8 (per latch) And the total CPD when n pcs of latch operate can be gained by the following equation: CPD (total) = 14 + 13 n 2000-07-04 5/7 TC7MH373FK Noise Characteristics (Input: tr = tf = 3 ns) Characteristics Quiet output maximum dynamic VOL Quiet output minimum dynamic VOL Symbol VOLP VOLV VIHD VILD Test Condition VCC (V) CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF 5.0 5.0 5.0 5.0 Ta = 25C Typ. 0.5 -0.5 Limit 0.8 -0.8 3.5 1.5 V V V V Unit Minimum high level dynamic input voltage VIH Maximum low level dynamic input voltage VIL Input Equivalent Circuit Input 2000-07-04 6/7 TC7MH373FK Package Dimensions Weight: 0.03 g (typ.) 2000-07-04 7/7 |
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